1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for accessing frame buffers used in providing output signals to output displays so that vertical lines are described rapidly.
2. History of the Prior Art
Computer systems use a buffer memory called a frame buffer for storing data which is to be written to an output display. The information in the frame buffer is written to the display line-by-line generally beginning at the upper lefthand corner of the display and continuing to the lower right-hand corner. One frame of information is followed by the next so that, as the picture in one frame charges to the picture in the next, continuous motion is presented.
Typically, a frame buffer is constructed of video random access memory (VRAM) which differs from conventional random access memory by having a first random access port at which the frame buffer may be read or written and a second line-at-a-time serial output port through which pixel data is furnished to the circuitry controlling the output display. Such a construction allows information to be written to the frame buffer while the frame buffer continually furnishes information to the output display.
One physical arrangement used for frame buffers arranges a number of banks of VRAMs so that a first pixel of a horizontal line which is to be dislayed is stored in a first VRAM bank, a second pixel on the line is stored in a second VRAM bank, a third pixel on the line is stored in a third VRAM bank, and so on through the last VRAM bank. Then the pixel storage starts over at the first of the VRAM banks. This arrangement allows very rapid writing of pixels describing a single horizontal line because a number of pixels may be written to the frame buffer together. Moreover, page mode addressing which allows more rapid addressing within a page of memory than typical random access of the frame buffer enhances this effect for horizontal lines.
However, the drawing of vertical lines on a display suffers drastically using the typical multiple banks frame buffer just described. This occurs because drawing a vertical line requires that the same VRAM bank of a frame buffer be used for each pixel of the line. Consequently, pixel accesses in the same VRAM bank must be addressed sequentially through the random access ports to describe the line. Since the same bank is being addressed to write to the frame buffer, there has been no way to make the accesses in parallel or to cause those accesses to overlap. The use of page mode accessing does not speed up the addressing of pixels describing vertical lines since the size of a page is typically only about a line or two of the display.
Drawing vertical lines has become more important recently with the advent of the various screen control programs which display a plurality of different application programs in a plurality of windows on the display. The number of vertical lines used by these screen programs makes the time required for their drawing less than trivial. It would, therefore, be advantageous to be able to accelerate the operation of drawing vertical lines on the output display of a computer system.